The present invention relates to a data driver, a display panel driving device, and a display device.
There is known a liquid crystal display (LCD) panel of active matrix type. This liquid crystal display panel includes scan (gate) lines arranged in parallel in the row direction, data lines arranged in parallel in the column direction, pixels placed at the intersections of the scan and data lines, and an active element (for example, thin film transistor (TFT)) provided in each pixel. When the active element is a TFT, the scan line is coupled to the gate electrode. Then, the data line is coupled to the drain electrode. One end of the liquid crystal capacitance, which is an equivalent capacitive load, is coupled to the source electrode. The other end of the liquid crystal capacitance is coupled to a common electrode line. A gate driver (scan line driving circuit) is coupled to the scan line, and a data driver (data line driving circuit) is coupled to the data line.
In the liquid crystal display panel, the scan lines are scanned in order from the top to the bottom by the gate driver, in order to apply a voltage to the liquid crystal capacitance from the data driver through the active element provided in each pixel. The data driver includes an output amplifier to apply the voltage to a plurality of data lines. The output amplifier includes a plurality of amplifier circuits. In the liquid crystal display panel, the alignment of liquid crystal molecules varies according to the voltage applied to the liquid crystal capacitance from the outputs of the amplifier circuits. Thus, the transmittance of light varies accordingly.
Recently the performance of the liquid crystal display panel has been improved, and a low power consumption, low noise, and high speed data driver is required to reduce the voltage of the circuit power supply. However, the low voltage of the circuit power supply can easily lead to an operation failure due to electrical noise. Thus, it is necessary to establish a circuit design by taking into account the importance of the noise problem. In particular, the data driver has a low voltage part including a logic unit and an interface unit, as well as a high voltage part including an amplifier circuit for driving the data line of the liquid crystal display panel. Thus, it is necessary for the data driver to reduce strong noise generated in the operation of the amplifier circuit, in order to prevent incorrect operation in the low voltage part.
As an example of the related art, Japanese Unexamined Patent Publication No. 2010-176083 (corresponding to US patent publication No. 2010/0194731(A1)) discloses a (data) driver and a display device. FIG. 1 is a block diagram of a data driver disclosed in Japanese Unexamined Patent Publication No. 2010-176083. The data driver includes an amplifier circuit drive unit 138 and a plurality of amplifier circuits 136-1 to 136-N. The amplifier circuit drive unit 138 outputs control signals CTR1 and CTR2 to the amplifier circuits 136-1 to 136-N. Each of the amplifier circuits 136-1 to 136-N outputs an output gradation voltage to a data line of a display unit (liquid crystal display panel) in response to the control signals CTR1 and CTR2. The amplifier circuit drive unit 138 includes a control circuit 140 and delay units 141, 142, and 143. The control circuit 140 outputs the control signal CTR1 to the delay unit 141. The control circuit 140 also outputs the control signal CTR2, which is the control signal CTR1 delayed by the delay unit 142, to the delay unit 143. The delay unit 141 sequentially delays the control signal CTR1, and outputs it to a first group of amplifier circuits 136-1 to 136-(N/2) that are one-half of the amplifier circuits. The delay unit 143 sequentially delays the control signal CTR2, and outputs it to a second group of amplifier circuits 136-((N/2)+1) to 136-N) that are the other half of the amplifier circuits.
FIG. 2 is a timing chart showing waveforms of control signals input to the amplifier circuits 136-1 to 136-N from an amplifier circuit drive unit 88. The control circuit 140 outputs the control signal CTR1 as a control signal. The delay unit 141 outputs the control signal CTR1 in order with a uniform delay to the first group of the amplifier circuits 136-1 to 136-(N/2). The delay unit 143 outputs the control signal CTR2, which is the control signal CTR1 delayed by an arbitrary amount by the delay unit 142, to the second group of the amplifier circuits 136-((N/2)+1) to 136-N in order with a uniform delay.